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Evaluating Impulse C and multiple parallelism partitions for a low-cost reconfigurable computing system.

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dc.contributor.advisor Duren, Russell Walker.
dc.contributor.author Li Shen, Carmen C.
dc.contributor.other Baylor University. Dept. of Electrical and Computer Engineering. en
dc.date.copyright 2008-12
dc.identifier.uri http://hdl.handle.net/2104/5280
dc.description.abstract Impulse C is a C-to-HDL compiler from Impulse Accelerated Technology that facilitates the introduction of software programmers, mathematicians, and scientists, into the realm of FPGA-based algorithm development for high-speed numerical computation. This thesis evaluates the Impulse C programming language and explores differing levels of parallelism across multiple, homogeneous, FPGA development platforms using the Aurora serial communication scheme. Impulse C and Xilinx IP cores are employed in the numerical computation of a neural network consisting of 27 inputs and 1200 outputs. The artificial neural network is capable of emulating an underwater acoustic environment and has been used to determine characteristic parameters of reflections from the ocean floor. Timing, logic utilization and ease-of-use are metrics used to evaluate Impulse C in the automatic generation of VHDL code for the network test application. Implementations with parallelism at the system level and at the intermediate (loop) level are explored as part of this study. en
dc.rights Baylor University theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. Contact librarywebmaster@baylor.edu for inquiries about permission. en
dc.subject Compilers (Computer programs) -- Evaluation. en
dc.subject C (Computer program language) en
dc.subject Field programmable gate arrays. en
dc.subject Neural networks (Computer science) en
dc.subject Adaptive computing systems. en
dc.subject Parallel processing (Electronic computers) en
dc.title Evaluating Impulse C and multiple parallelism partitions for a low-cost reconfigurable computing system. en
dc.type Thesis en
dc.description.degree M.S.E.C.E. en
dc.rights.accessrights Worldwide access en
dc.contributor.department Engineering. en


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